Fully integrated microprocessor controlled radar display

ABSTRACT

A special purpose decoder and display unit is designed to present special format radar signals for training. Several display formats ease operator workload while acquiring desired radar formats. A reference tone is recorded along with radar signals on a tape and a phase locked oscillator receives the reference tone which has the same fluctuations that the recorded radar signals have. A controlled computer and the phase locked oscillator feed their signals to a frequency synthesizer that creates a fine tuned signal based on the output signals of the phase locked oscillator and the computer. A timing generator is coupled to receive the output of the frequency synthesizer and it generates special purpose timing signals which are fed to a display. A video input receives radar signals coming from the tape, for example, to generate a sense directed, gain controlled video signal. A planned position indicator converter receives the gain controlled video signal and processes the signal from polar to rectangular coordinates in accordance with directions from the control computer so that a display unit can appropriately show the information contents of the video input signal without the wow and flutter that might otherwise be attributable to speed inconsistencies of the tape.

STATEMENT OF GOVERNMENT INTEREST

The invention described herein may be manufactured and used by or forthe Government of the United States of America for governmental purposeswithout the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION

This invention relates to radar displays and the means by which improvedradar displays are presented. More particularly the invention concernsthe display of radar information in a variety of formats in a selectivemanner without calling for needless complexity of associated equipments.In yet greater particularity the invention provides for the display ofradar information, for example, for training purposes, having the radarinformation recorded on a tape along with a recorded reference tone suchthat the display is not adversely affected by speed inconsistencies ofthe tape that would otherwise introduce what is commonly referred to aswow and flutter in the displayed radar images.

The evolution of radars has been a nearly non-stop effort since itsinception. Increased capabilities that are currently practiced are farbeyond what, only a short time ago, was thought to be impossible. Thestate-of-the-art continues to advance at a rate which makes the trainingof operating personnel more and more difficult.

Complex expensive systems operationally disposed cannot be takenoff-line for routine training activities nor can they be used as a toolto give needed simulations for sharpening the skills in situations whichvary from the ordinary. Although some training aids have been designedwhich keep pace with systems in the field, they have been expensive,complex and require discrete special purpose circuitry. The hardware andassociated software also compounded the problems of maintenancepersonnel since these equipments also needed to be serviced. In one formor another the various formats could be presented yet usually increasedcomplexity of the overall system was the price that had to be paid.There seems to be little available in the sense of a training aid orsystem calibration device which can use taped radar presentations thatcan compensate for the imperfections of the recording and playbackcircuitry.

Thus there is a continuing need in the state-of-the-art for a costeffective, relatively uncomplicated display and its associated controlunit which can accommodate taped radar information and show it in avariety of formats.

SUMMARY OF THE INVENTION

The present invention is directed to providing an apparatus for decodingand displaying radar signals in different formats. A means provides areference frequency source on a tape alongside and in the same timeframe as a means of providing a source of video signals on the sametape. A means is coupled to receive the variable reference frequency foroutputting a signal that is phase locked to the variable referencefrequency. A control computer and the phase locked outputting means arecoupled to a means for synthesizing a fine tuned signal based on theoutputs of the phase locked signal generating means in accordance withthe signals received from the control computer. A means is coupled toreceive the output from the synthesizing means to generate specialpurpose timing signals as directed by the control computer and the meansis disposed to receive the video input signal from the video signalproviding means for producing a sense directed gain controlled videosignal. A plan position indicator converter is coupled to receive thevideo output of the producing means and to process the video output frompolar to rectilinear coordinates in accordance with signals receivedfrom the control computer. A display is coupled to the plan positionconverter for showing the radar signals in different formats withoutobjectionable fluctuations in response to instructions coming from acontrol panel.

A prime object of the invention is to provide an improved radar display.

Yet another object of the invention is to provide a display capable ofshowing taped radar information without wow and flutter that may becaused by inconsistencies of the tape rate.

Yet another object is to provide an improved radar display having thecapability for providing information a number of different formats.

Still another object of the invention is to provide a control unit for adisplay that accommodates taped radar display information and presentsit in different formats.

Still another object of the invention is to provide a display controlunit that is compact in size and of reduced complexity to reduce thecost associated with procurement and training.

Yet another object is to provide a display control unit for radardisplays that is adaptable to a commercially available display.

These and other objects of the invention will become more readilyapparent from the ensuing description and drawings when taken with theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram representation of the principalconstituents of the training radar display.

FIG. 2 depicts a bus diagram of the training radar display.

FIG. 3 sets forth the schematic of the video gain control circuitry.

FIGS. 4 a and 4 b are schematic diagrams of the details of the referencetone, phase-locked oscillator.

FIGS. 5 a and 5 b show the details of a schematic diagram for thefrequency synthesizer.

FIGS. 6 a and 6 b are detailed schematic diagrams of the data extractorcard.

FIGS. 7 a and 7 b are schematic diagrams of the pulse position indicatorconverter.

FIGS. 8 a and 8 b show schematic diagrams of the microcomputerfabricated in accordance with the teachings of this inventive concept.

FIGS. 9 a and 9 b show the control panel in schematic diagram form.

FIG. 10 shows the front panel control wiring diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1 of the drawings a training radar display 10receives signals representative of visual information and provides for ashowing of the information on a display 100. In this regard the trainingradar display is to be considered as a special-purchase decoder anddisplay unit designed to present special-format radar signals. Thesignals are displayed in several display formats for easing operatorworkload while acquiring desired radar formats.

The display can be one of several commercially available units; however,for purposes of realizing the capabilities of the training radardisplay, a Model 1340aXY display marketed by Hewlett-Packard Corporationhas been selected to provide the video displays in a variety of formats.A thorough understanding of the operation and makeup of theHewlett-Packard display can be obtained from the operating and servicemanual, manual part No. 01340-90901 obtained from Hewlett-Packard Co.,Colorado Springs Division, 1900 Garden of the Gods Road, ColoradoSprings, Colo., USA.

Details of operation of the display unit can be obtained from themanual; however, the unit has a P-7 phosphor, which provides thenecessary long persistence that a PPI radar display requires. Inaddition a light-emitting diode alphanumeric display is provided to showvarious messages and numeric data that are extracted from an incomingsignal.

The prime function of the training radar display is to properly format,condition, and display the incoming video signals. The video signals canoriginate on, for example, a magnetic tape which contains all theinformation of a radar display. Along with the video signals on the sametape and in the same time frame, a video information tone comes in firstto the video automatic gain control circuit 20 on to a pulse positionindicator converter 30 and onto display 100. All system control ishanded by a computer 40 which partially means that the display formatcontrol and interaction with the operator of the training radar displayalso are system control functions handled by the computer. Any digitalpulses that are specially recorded with the radar video and aretherefore present in the incoming video signal, are extracted by a dataand doublet detector 50 which is actually a part of a data extractorcircuit 60. In this regard the separate functions are depicted forpurposes of clarity in FIG. 1 it being understood that later figures inthe drawings, FIGS. 6 a and 6 b show the details of the data extractorand data and doublet detector as a combined unit.

The main system timing is derived from either a crystal reference orfrom a reference tone coincidentally recorded on the wideband tapecontaining the signal of interest appearing at the video input to videoAGC 20. All precision frequencies and timing signals are derived fromthe crystal reference or from the reference tone by a phase lockedoscillator 70. All precision frequencies and timing signals are derivedfrom the crystal reference or reference tone and are generated from a 10MHz signal within a frequency synthesizer 80 which is phase locked toeither the reference tone or the phase-locked oscillator 70.

The various circuits in the training radar display are separatelymounted on cards and have been designed to operate on common busses inorder to ease interconnection requirements. These buses have beenavoided in FIG. 2 of the drawings to avoid unduly complicating it. FIG.2 shows the bus routings noting that a first bus is provided thatcontains signals that are common to all the circuitry within video AGC20, phase locked oscillator 70 and plan position indicator converter 30.A second bus is used to interconnect data extractor circuit 60 and thecircuitry of frequency synthesizer 80. A third bus is required forcomputer 40 because the bus size is limited to fifty wires and thecomputer requirements call for extensive input and output terminals.

Because the three busses mentioned above are filled by the describedcircuit components, interconnections to a front panel 90 are handled bya fourth bus. All required interconnections are done on a motherboardwith wire wrap.

The function of video automatic gain control circuit 20 is to buffer theinput video that comes into the training radar display unit, see FIG. 3.If necessary this circuit also provides video inverting, and anautomatic gain control function designed to keep the circuit outputvideo constant. The circuit also provides a digital output, which givesa simple one-bit analog-to-digital conversion of the input signal.

Referring to FIG. 3 note that the function of R19 and R18 are the sameas those of a voltage divider and an input-line termination. The voltagedivision ratio is 4:1 and C17 provides the AC coupling into U5. Thefunction of U5 is to provide variable gain for controlling the automaticgain control. The U5 output is also AC-coupled with a fast-time constantcapacitor C13. U3 provides the inverting or noninverting function to theinput. The state of switch U3 is determined by the front-panel operatorcontrol called invert. Pull-up resistor R11 supplies a logic “1” whenthe front-panel switch is open. Inverting or noninverting is actuallyaccomplished by U2, whether the input is supplied to the inverting inputor to the noninverting input.

The amplifier gain is set to approximately 10. Diode D1 provides signalclamping to the ground. The combination of D1 and D2 detects the videooutput and holds the peak value of that value on capacitor C14. C14charge time on a signal peak is very fast through resistor R14. However,in the absence of a signal, the charge on C14 leaks away through thecombination of R14 and R13, with R13 being a large resistor. The decaytime constant is long. This peak voltage is followed by amplifier U4with a voltage gain of approximately fifteen. The resultant amplitude isrepresentative of the input signal peaks and is fed back to the U5gain-control input. This input forms the total feedback loop, controlsthe output gain, and holds this gain constant. An output sample iscoupled through C1 to integrate at circuit U1. The function of U1 isthat of a comparator with the threshold level set by R1.

Looking to phase-locked oscillator circuit 70 of FIGS. 4 a and 4 b, thecircuit depicted provides the timing signals for the entire trainingradar display. The timing signals are derived from a tape referencetone. That is to say, the reference tone shares space with the incomingvideo signal within the same time frame or time reference.

The tape reference tone is either a 50, 100, or 200 kHz sine wave thatis terminated into a 300 ohm resistor R28 on the circuit. An inputlimiter consisting of U8 and diodes D1 and D2, limits the input signalwhile providing gain.

A bandpass filter separates the input signal to reduce any out-of-bandcomponent. The filters include resistors R11, R12, and R10, andcapacitors C9 and C10 if the input frequency is 100 kHz. If the operatorselects a reference-tone frequency of 50 kHz the components involved areresistors R17, R18, and R19 plus capacitors C13 and C14. For the 200 kHzselection the components are resistors R14, R15 and R16 and capacitorsC11 and C12. The heart of this filter section is the multi-inputoperational amplifier U5.

The input selected is determined by a frequency select switch found onfront panel 90. The active-filter output appears on N10. This output isfurther limited by U1 to a TTL logic, level square wave. The square wavemay or may not be exactly 50% duty cycle. The rest of the circuitrydemands that there be a perfect 50% duty cycle. In order to form a 50%duty a divider U2 is employed. The divider transitions between logicstates only on the positive edge of the U1 signal. This output(available on a test point E1) forms the basis for the phase-lock loopof this circuit.

A signal is then passed into U4 (the actual phase-lock loop integratedcircuit) as the reference input. Pin 4 on U4 is the 10 MHz low-level,phase-locked signal. Transistors Q1 and Q2 buffer that low-level signalinto a signal compatible with TTL levels.

This process forms a clock for the entire display when thereference-tone input is used. In order to complete the phase-lock loopthe 10 MHz signal is divided by U9, U10, and U11 to one of threefrequencies. These three frequencies are 25 kHz which is available onpin 13 of U11; 50 kHz, available on pin 14 of U11; and 100 kHz availableon pin 2 of U11. One of these three signals is selected by multiplexerU12. The U12 output on pin 15 and on test point E2 is used to feed backinto U4 as the phase-lock reference. U4 compares this phase-lockreference with the input signal from the reference-tone input andadjusts the 10 MHz output to keep up with any wow and flutter that maybe present in the reference-tone input.

Circuitry composed of U2 and U3 monitors the reference-tone input todetermine when phase-lock has occurred. If phase-lock has occurred, thenthe circuit assumes that there is a reference-tone present. Thereference-tone presence line on the screen falls to the lower level ofthe screen (negative logic) and enables the phase-lock 10 MHz signal toexit the circuit on pin 50. If there is no lock on the circuit, theassumption is that the reference-tone is not being supplied and aninternal crystal U6 supplies a stable 10 MHz signal for the remainder ofthe training radar display. Chokes L1, L2, L3, and their associatedcapacitors effectively bypass the power supplies for this circuit.

The frequency synthesizer 80 depicted in FIGS. 5 a and 5 b has twodistinct functions. Each function will be discussed separately. Thefirst function is to divide a 10 MHz master clock into a frequency thatis only slightly adjustable. This 30 kHz frequency must have a digitalresolution that is finer than a normal 10 MHz would allow. Generally, adigital divider has discrete frequency steps, with the finest of eachstep being 100 nanoseconds. However, with a unique interpolatingfrequency divider, the apparent resolution can go down by two orders ofmagnitude. The first frequency division takes place in U2, U3, and U4and is a straightforward digital divider. This divider is variable inits division ratio. U3 and U2 are fixed; U4 is preset from the contentsof U1. The contents in U1 are determined by a system computer 40.

Integrated U7 and U9 are rate multipliers that receive the approximate37 kHz from U2. U7 and U9 generate an interpolate frequency that goesfrom 0 to 37 kHz depending on the input to integrated circuits U7 andU9. These integrated circuits come from U6, U8, and U10 and in turn areset by system computer 40.

The effect of the interpolate frequency is to subtract one clock pulsefor every interpolate pulse. Pulse subtraction is done by the clockdeleter circuit formed by U5. The instantaneous frequency that isgenerated by this circuit is 37 kHz. However, when the clock deletereffect is considered over a longer time, the resolution in the frequencythat can be generated by this string of integration circuits is down to25 ps. The outputs from this circuit appear on pins 11, 13, and 29.These pins are all of the same frequency, but they have differentduty-cycle signals that are used in different ways throughout theremaining parts of the circuit to be discussed.

The second function of the circuitry of frequency synthesizer 80 is tohandle the input digital data derived from the analog video signal. A500 kHz clock is generated by U21 and U22. The function of this clock isto shift the digital data into a shift register, which is formed by U14and U19. A digital representation of the input-pulse waveform is presentat any instant in time in U14 and U19. U15 and U20 form a gate array,which is preprogrammed to look for the proper pulse width andinterpulsed spacing of the input digital data.

An ancillary function of this card is to phase detect the digital bitsthat appear in the video input with respect to the master timing system.This phase detection is done by the sample-and-hold integrated circuitU12. A triangular wave present on pin 3 of U12 is sampled whenever adigital “1” is present. If the timing is correct, the resultant outputvoltage held on the output of U12 (pin 5) will be midway between the twovoltage levels present on the comparator's input U13. However, if thedigital “1” is either early or late with respect to the input trianglewave coming into pin 3 of U12, then the output voltage on pin 5 willeither raise or lower and trip one of the two error thresholdsassociated with U13. The threshold comparator outputs will generatefrequency errors called ERRORA and ERRORB, which are monitored by thesystem computer and can be used to raise or lower the synthesizerfrequency on the frequency interpolator. By this method the totaldisplay timing is phase locked to the input video signal.

This raising and lowering is done by pulses on the UPFREQ and ENFREQinputs to this circuit. These two inputs are counted up or down by thefour counter integrated circuits, U1, U6, U8 and U10. The outputs ofthese counter integrated circuits form the preload for U4 and the ratemultiplication factor for U7 and U9. L1, L2, and L3, and theirassociated capacitors effectively decouple the power supply from thiscircuit.

The function of data extractor 60 and data and doublet detector 50 firstidentified with respect to FIG. 1 are examined in detail with respect tothe schematic diagrams of FIGS. 6 a and 6 b. And the functions arethreefold. The first function is that of PRI generation. The 37 kHzsignal from frequency synthesizer 80 enters on pin 11 and is divided byU9 and U8 to one of three division ratios. The division ratio selectiondepends on the radar display pulse repetition interval.

Programmable gate array U7 takes the U9 and U8 counter states andprovides for output signals with prescribed wave shapes to the rest ofthe circuitry. Outputs 3 and 2 from U7 provide the blanking pulsescalled BLANKP and BLANKA. BLANKP is the PPI blanking pulse and has along blank period so as to present only valid radar picture data. BLANKAis a very short pulse used only to return the display sweep to the edgeof the screen in preparation for a second sweep. Other outputs from U7form various timing functions. Output “1” (01) is the preset pulse thatturns counters U8 and U9 back to the beginning so that the process maystart over. In conjunction with the 37 KHz input signal, output 4 isused to clock the data-load shift registers U2 and U5 in preparation fordata recovery by computer 40.

The input data appears on pin 49 and is buffered and held by U19. Atproper time and in proper phase with the input signal, shift registersU2 and U5 will move the digital portion of the waveform into the shiftregister. This data is held and sampled by U3 and U4. U3 and U4 areunder computer control and form a sequential data recovery system. Thecomputer interrogates this circuit and reads the data from U3. After thedata has been successfully read from U3, a pulse on the select linechanges the output data to data held by U5. This data is buffered out byintegrated circuit U4. The computer is able to read all of the digitaldata with two data read operations.

Integrated circuits U10, U11, U12, U13 and U6 form a state machine,which is used to find the proper sync pulse position and to rephasecounters U9 and U8. Once the operator has manipulated the hold controlto make the waveform stationary on the “A” sweep display, this circuitryexamines the input signal to find the sync pulse. Once the sync pulsehas been successfully found, the circuitry rephases the main counters U8and U9.

The PPI converter 30 as shown in FIGS. 7 a and 7 b has as one of itsmain functions to provide analog sweep information and Z-axis videoinformation to create the necessary picture on the training radardisplay 100. The inputs to this circuit are both digital and analog. Thedigital inputs arrive from computer 40 as part of the data bus. Theseinputs provide three different functions with the first and most usedfunction being the sweep angle.

There are twelve bits required to resolve this sweep angle function. Thefour most significant bits are unbuffered and go directly to U1, with U1being a special module that takes digital-angle and analog-rangeinformation and does a polar-to-rectilinear conversion. (The outputsfrom the PPI circuit are R sine data and R cosine data. These outputsdrive the X and Y deflection plates in the CRT display in display 100.)The least significant eight bits are buffered by U6 and held in adigital-to-analog converter integrated circuit U5. The data is strobedinto this integrated circuit by the signal RSTROBE and the computersupplies the proper digital bits to strobe U5. The U5 is able to providethe analog current that corresponds to the digital input on pin 1. U2 isconfigured as an integrator and provides the range sweep to U1. Therange sweep is properly timed by sweep switch U12. This circuit isdriven by the sweep blanking pulses, which will be discussed below.

When the sweep switch is open, U2 is able to charge capacitor C19 in alinear fashion at a rate that depends on the input current supplied byU5. When the end of the sweep arrives, sweep switch U12 closes, shortingcapacitor C19 and simultaneously interrupting the input current sourceto U5 called V ref. Proper sweep-switch timing is dependent on theblanking pulses. The selection of the proper blanking pulse, eitherBLANKA or BLANKP, is made by the input selector switch U4, which isunder control of computer 40.

To summarize the operation of the sweeping circuits, computer 40 firstsets an angle where the sweep is to occur, then strobes the proper rangerate into U5. The computer then selects the proper length of sweepblanking, either BLANKP or BLANKA, and the rest of the timing is underthe control of BLANKA or BLANKP. The third and last function of thecircuit of FIGS. 7 a and 7 b is mode control, which is latched and heldin integrated circuit U9. In order to store the mode of operation onthis card computer 40 must present the mode on the data bus and thenstrobe U9 with a signal called display control strobe (DSS). Of theeight bits presented to this latch, only five are used on this circuitthus leaving three available for other uses on other circuits.

The five circuits used to control this circuit are the blanking mode,whether that be “A” sweep or PPI sweep; the Z-axis mode, which is eithervideo or the Z-axis (as in a standard PPI presentation) or constantintensity, which is required for the “A” sweep mode; range rings, whichcan be either on or off; and the analog offsetting of output X and Ywaveforms, which requires two digital signals to properly set analogswitch U8. The first portion of switch U8 is as required by the “A”sweep; X offset in a minus direction is needed to put the starting pointof the sweep at the left side of the screen. The Y-axis DC offset is setat zero in this mode. The second position is used in the standard PPIsweep where no offset is required in either the X or the Y direction.Both inputs to switch U8 in the second position are connected to ground.The third position is used for the offset joystick control. In this modethe X-joy and the Y-joy inputs, which are buffered by U7, are connectedto the offset inputs of U1 through switch U8. The fourth position isused for signals A367 and A403 and requires an offset at the start ofthe sweep to the bottom of the screen. In this mode, a voltage issupplied to the Y-offset pin of U1 and the X-offset pin is set toground.

The AGC video signal coming from video AGC 20 is buffered and the inputlevel reduced by a factor of two. Integrated circuit U13 is used as aninverting amplifier. This video, or minus video as it is called on theschematic, is then available as the offsetting voltage in the Ydirection when in the “A” sweep mode. This is a complicated way ofdescribing the standard oscilloscope mode of operation where the videonow appears as up and down movement of the beam as the beam traces fromleft to right. The minus video is AC-coupled into integrated circuitU14, which is a gain control integrated circuit where the gain ismanually set by the gain control on the front panel.

The output of U14 is coupled through mode control switch U12. Thefunction of this switch is to either interrupt or supply the video tothe Z-axis depending on the mode of operation. If the training radardisplay is in any of the PPI modes, the video becomes a signal requiredon the Z-axis to modulate the intensity of the CRT beam in display 100.However, if the training radar display is in the “A” sweep mode, theintensity required on the Z-axis becomes a constant. The resultantwaveform passes through half of integrated circuit U11. This is theintegrated circuit that is used to intensity-modulate the Z-axis duringthe range-rings mode of operations.

To understand how range rings occur, an understanding of integratedcircuits U3 is necessary. Integrated circuit U3 is a dual functionintegrated circuit, with the first function being a divide-by-tencounter, and the second being a very short-period one-shot that istriggered by completion of the divide-by-ten operation.

At the beginning of sweep, sweep blanking is high, and the counter chainin U3 is reset on pin 2. As soon as the sweep starts, sweep-blankingdrops to a logic low and U3 begins to count the 37 kHz signal (37 kHzhaving been selected as the clock throughout the training radar displaybecause of the relationship with the speed of light). In other words, ifthe time for the radar pulse to move four kilometers and return weremeasured, this time would be exactly the same as the period of a 37 kHzclock. The result of dividing 37 kHz by ten is one pulse every 40kilometers, which coincides with the range-ring interval selected. Atthe end of 40 kilometers, the one-shot which is the second half of U3fires, and generates a short pulse on pin 10. This pulse switches therange ring switch U11 momentarily so that the Z-axis video is changedfrom normal, video input to a 2½-volt positive voltage, which has theeffect of putting a bright dot on the screen.

This range-ring function can be controlled by the ring's-mode switch onpin 9 of U3. The divide-by-ten counter can be enabled or disabled undercomputer control and can effectively turn on or turn off the range-ringfunction. The output of the range-ring's switch, on pins 14 and 16 ofU11 is supplied to the other half of U11, which is called the blankerswitch.

It is necessary to turn off the intensity whenever the beam is to bemoved from the outer part of a sweep back to the beginning of a sweep.This step keeps the retrace from distorting or overriding the radarpicture that is displayed. The function in U11 is to momentarilydisconnect the video and supply a minus voltage (approximately minus onevolt) that effectively turns off all beam current in the cathode raytube within display 100.

The only function remaining for the circuit depicted in FIGS. 7 a and 7b is to buffer the Z-axis information, which is supplied both to thelocal cathode ray tube and the remote cathode ray tube, with ahigh-speed, high-current buffer (U10). L1, L2, and L3, and theirassociated capacitors form the power-supply bypass required on thiscircuit.

The circuitry of computer 40 is set forth in FIGS. 8 a and 8 b. It formsthe heart of the training radar display unit. The circuitry is based onmicroprocessor technology (MC6800), and the actual microprocessorintegrated circuit is an MC6802. The philosophy used in developing thiscircuitry was to provide the maximum number of parallel input and outputlines while the circuitry performed necessary hardware timing functions.Enough address space was included for 4,096 bites of program, 2,048 ofwhich are actually used in the training radar display program. Theinput/output (I/O) lines are unbuffered and are provided by the MC6821.The actual integrated circuits on the board that perform the I/Ofunction are U6, U7, and U8. Of these integrated circuits, U6 is onlypartially used with the limitations because of the low number of pinsavailable on the edge connector.

The program storage is in erasable, programmable read-only-memory(PROM), part No. 2716. The hardware timer on this board is an MC6840.

In actuality, three timers are available for access by themicroprocessor. The address space partitioning is redundant, meaningthat not all of the sixteen address lines are used, and the program canreside only in address spaces FOOO HEX through FFFF HEX. The variousother address space allocations are notated on the schematic drawing ofFIGS. 8 a and 8 b. The unique feature incorporated in this circuitry isthe use of the watchdog timer. The purpose of the watchdog timer is todetect a wild, free-running program, meaning a program not following thedesired program path. When this is detected the microprocessor isautomatically restarted. The method used to achieve this restart processis to use one output line on U6 as a watchdog clock. This watchdog clockmust restart the watchdog timer every 20-ms or the main reset 1-shotwill fire, thus resetting the microprocessor. This 20-ms watchdog clockis generated by the training radar display software. When the program isrunning properly pulses can be seen coming out of pin 10 on U6 at aninterval of 20-ms or faster. In actual operation the pulses come at asporadic rate, sometimes more often than 20-ms. Access is provided atthe card edge for both the nonmaskable interrupt (NMI) and the interruptrequest lines (IRQ) on pins 49 and 50, respectively.

Since these lines tie directly to the microprocessor, erratic operationcan happen if the lines are misused. The proper configuration for thewire-wrap patching, which is made up of test-point pins E5, E6, E7 andE8, is for E5 and E6 to be connected to E8. This interconnection enablesinterrupt requests, which are generated by the I/O integrated circuitsand from the timer, to be vectored to the IRQ on the microprocessor.

Noting FIGS. 9 a and 9 b, the function of the circuitry associated withfront panel 90 is multipurpose. The electronics function is numericdisplay generation with mode and range switch interfacing. According tothe schematic seven data-bus lines are brought onto the card for severaluses. These data bus lines are buffered by integrated circuit U4 anddrive multi-digit alphanumeric displays U1, U2, and U3 in a parallelconnection. These displays each contain memory latches and displaydecoders, plus the light emitting diode (LED) display elements. Thereare four digits within each unit, and the digit address is selected byA0 and A1 on each of the integrated circuits. A counter integratedcircuit U6 is used to sequentially address all twelve digits startingfrom the right-hand end of the digits and proceeding to the left.

In order to write a string of alphanumeric characters the counterintegrated circuit is first reset with a pulse on the master reset (MR)line, pin 21 on the connector located on this circuit. The circuit thenselects the digit in U3 closest to the right-hand end. Once the properAmerican Standard Code for Information Interchange (ASCII) code for thedisplayed digit is entered on the seven data lines, a write pulse isstrobed on the WR line. This pulse performs two functions: (1) it entersdata into the memory of U3, and (2) it increments the counter of U6,which now addresses the next digit waiting for the proper data to bestrobed into that digit's memory.

This sequence of events continues until all twelve digits have beenfilled. A safety feature is provided so that multiple strobing beyondtwelve digits will not override any of the digit's information that hasalready been entered. The function of providing a safety is performed bydisabling the counter integrated circuit at its maximum count.

Other electronic functions occurring are related to the mode switch andthe range switch. In order to limit the number of lines required atcomputer 40 for reading the mode switch or the range switch, theswitches are sampled by the computer and when the proper mode sample isoutput from the computer, a mode indicator MODIND will be a logic “0”.An examination of U9 and U10, particularly U9, will reveal that modeswitch S3 has four lines and is hex encoded. There are sixteen possiblepositions in switch S3 and the binary representation of the positionselected appears on the four outputs of the mode switch. When thecomputer puts the same binary representation on D0, D1, D2 and D3,integrated circuit U9 will indicate equivalence between the switchinputs and the computer input by generating a logic “1” on theA-equals-B output. This, then is ORed with the similar output from thecomparator looking at the range switch. Either of these comparisonsbeing equal will cause the mode indicator line to be a logic “0”.Therefore, the computer can query either or both of the switches in asequential manner until the mode indicator notifies the computer thatthe proper setting has been met.

Other functions of the circuitry are merely interconnections for variousfront-panel controls. For example, the rate control connector is anoptical tachometer that requires five volts for power and provides twoquadrature square waves on rate A and rate B outputs. These outputscorrespond to the rate at which the hold control is being turned. Thecomputer then analyzes these two lines to determine which way the knobis being turned and at what speed it is being turned.

Looking to FIG. 10, power for the training radar display decoder isderived from the display 100, in this case the HP1340A. The displaywiring for the training radar display has been modified to eliminate thecapability of accommodating various input line voltages.

The decoder electronics draw approximately 2 A and are fused on the rearpanel with 3 A fast-blow fuse. After switching the front panel powerswitch, the display unit power is passed to the main power supply, tothe fan, and to the rear-mounted display fuse. This fuse is the required0.6 A slow-blow fuse, which is normally mounted internally to thedisplay unit the power for the display unit is supplied back throughconnector P6.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

1. A training radar display for decoding and displaying radar signals indifferent formats, comprising: a variable reference frequency meansincluding a tape having a reference tone recorded thereon for providinga reference frequency being variable in accordance with rate of travelfluctuations of the tape, the variable reference frequency thereof iscaused by fluctuations of the tape playback rate; means connected to thevariable reference frequency means for generating a signal that is phaselocked to the variable reference frequency; means for generatingdirecting signals; means coupled to the phase locked signal outputtingmeans and the directing signal's generating means for synthesizing afine tuned signal based on the output signal of the phase locked signalgenerating means in accordance with the signals received from thedirecting signal's generating means; means providing video signals;means disposed to receive a video input signal from the video signalproviding means for producing a sense directed gain controlled videosignal; a plan position indicator converter coupled to receive the videooutput of the producing means and to process the video output from polarto rectilinear coordinates in accordance with signals received from thedirecting signal's generating means; means coupled to the plan positionindicator converter and to receive the special purpose timing signalfrom the using means for presenting a display thereof; and a controlpanel connected to the directing signal's generating means, the videoinput producing means, the plan position indicator converter andpresenting means to provide for input direction from the directingsignal generating means.
 2. An apparatus according to claim 1 in whichthe video signal providing means is a recording on the same tape as thevariable reference frequency means alongside and in the same time framethereof.
 3. An apparatus according to claim 2 in which the phase lockedsignal outputting means is a phase locked oscillator and the directingsignal's generating means is a control computer.
 4. An apparatusaccording to claim 3 in which the synthesizing means is a frequencysynthesizer, the using means is a timing generating and the presentingmeans is a video display unit.
 5. An apparatus according to claim 4 inwhich the phase locked oscillator is fabricated to generate a 10 MHzsignal and the frequency synthesizer is composed of elements to generatea 50 KHz signal in response thereto and the control computer.
 6. Anapparatus according to claim 5 in which the phase-lock outputting meansincludes means for determining when phase-lock to the variable referencetone has occurred.
 7. An apparatus according to claim 6 in which thephase-lock outputting means includes an internal crystal generating astable reference frequency tone that is coupled to the phase-lockdetermining means to be actuated when no variable reference tone isbeing received.
 8. An apparatus according to claim 7 in which theinternal crystal passes a 10 MHz stable signal for the interconnectedcircuitry of the display control unit to permit operation thereof inother modes than when a variable reference tone is provided.
 9. Anapparatus according to claim 8 in which the plan position indicatorconverter provides analog sweep information and Z axis video informationto create the picture on an interconnected display unit.